ANTI-TAMPER DIGITAL CLOCKS - AN OVERVIEW

Anti-Tamper Digital Clocks - An Overview

Anti-Tamper Digital Clocks - An Overview

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The prior description of the disclosed embodiments is delivered to enable anyone skilled in the art to create or make use of the existing creation. Several modifications to these embodiments are going to be conveniently apparent to These expert while in the artwork, along with the generic ideas outlined herein might be placed on other embodiments without departing with the spirit or scope on the invention.

In other a lot more in depth aspects of the creation, Just about every of the plurality of delayed monotone signals comprises possibly a a single or maybe a zero. The Consider circuit may possibly decide whether the quantity of ones while in the plurality of delayed monotone indicators differs from the water amount quantity by greater than a predetermined threshold.

The h2o degree number can be determined determined by delayed monotone signals from one or more preceding clock Appraise time. The plurality of resettable hold off line segments could comprise taps together a delay line. Alternatively, the plurality of resettable delay line segments comprises parallel hold off lines.

A further delay line segment could possibly have N delay components that produce the utmost delayed monotone signal 230-N. AND gates within the delay traces may well each have a reset input RST to reset the line involving the delay aspects to established the hold off line to an initial regarded point out.

Priority day (The priority day is undoubtedly an assumption and isn't a lawful conclusion. Google has not performed a lawful Examination and can make no representation as towards the accuracy on the date listed.)

22. An apparatus for detecting clock tampering, comprising: a first circuit that gives a primary monotone sign during a primary clock Examine time period related to a clock;

What exactly is claimed is: one. A method for detecting clock tampering, comprising: supplying a plurality of resettable delay line segments, whereby resettable hold off line segments among a resettable hold off line segment affiliated with a minimum hold off time and also a resettable hold off line segment linked to a highest delay time are Each and every associated with discretely rising hold off instances;

A monotone signal is supplied in the course of a clock evaluate period of time connected with a clock. The monotone sign is delayed employing Every single from the plurality of resettable hold off line segments to deliver a respective plurality of delayed monotone signals. The clock is accustomed to induce an Assess circuit that takes advantage of the plurality of delayed monotone signals to detect a clock fault.

34. The apparatus for detecting voltage tampering as outlined in declare 33, wherein the water amount amount is set determined by delayed monotone signals from a number of preceding Appraise time.

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The hold off concerning the reset operators of another sensing circuits might be less stringent and will be based on the best appropriate working frequency.

Since the clock needs to be plugged in to work, the CL100 have to generally be put in more than an outlet making sure that the entry panel covers the outlet (batteries can be used like a backup electric power source in case of electrical power outage.)

A different facet of the creation may perhaps reside within an apparatus for detecting clock tampering, comprising: suggests 250 for giving a monotone signal 220 throughout a clock evaluate period of time 310 connected to a clock CLK; usually means 210 for delaying the monotone signal employing a plurality of resettable delay line segments to produce a respective plurality of delayed monotone signals 230 having discretely increasing hold off situations amongst a minimal delay time along with a most delay time; and suggests 240 for utilizing the clock CLK to cause an Appraise circuit 240 that utilizes the plurality of delayed monotone signals to detect a clock fault.

eighteen. The equipment for detecting clock tampering as defined in declare 15, wherein the Appraise circuit establishes whether or not the volume of kinds while in the plurality of delayed monotone signals differs from a drinking water stage selection by a lot more than a predetermined threshold to detect a clock fault.

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